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National Repository of Grey Literature 2 records found  Search took 0.01 seconds. 
A Test Interface for Integrated Circuits with the Small Number of Pins
 Tománek, Jakub ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This study explores the possibilities for reducing the number of pins needed for scan mode interface. In the first part of this paper the existing solutions and methods that are usable for this purpose are described. Specific four pin, three pin, two pin, one pin and zero pin interfaces are designed in second part. Advantages and disadvantages of existing solutions and methods as well as designed and proposed interface are summarized in the conclusion.
Detailed record
A Test Interface for Integrated Circuits with the Small Number of Pins
 Tománek, Jakub ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This study explores the possibilities for reducing the number of pins needed for scan mode interface. In the first part of this paper the existing solutions and methods that are usable for this purpose are described. Specific four pin, three pin, two pin, one pin and zero pin interfaces are designed in second part. Advantages and disadvantages of existing solutions and methods as well as designed and proposed interface are summarized in the conclusion.
Detailed record

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